STM32F4 clock configuration

__________________________Clocks______________________________

Clock sources :

* HSI  : High speed internal  16MHZ +/- 1% ( the Default clock )
* HSE : High speed external 8MHZ
* PLL : Phase locked loop    CLK times 2 to 16  ( multiplier )
* Secondary sources :  * LSI  : Low speed internal 32 KHZ watch dog timers clock
                                     * LSE : Low speed external 32;768 KHZ

Clocks:

system clock : the core clock                              max  168 MHZ
AHB  : Advanced high performance Bus            max  168 MHZ
APB1  : Low speed advanced peripheral Bus      max  42   MHZ
APB2  : High speed advanced peripheral Bus     max  84   MHZ


USB OTG FS
RNG  ( random number generator )
SDIO

I2S have their own internal clock : PLLI2S ; or ext source

MCO1 : output clk "PA8" from HSI, LSE, HSE, PLL /1 to 5
MCO2 : output clk "PC9" from HSE, PLL, PLLI2S, system clock  /1 to 5



use the config tool to generate "system_stm32f4xx.h"  include this file to have access to 3 functions :

SystemInit()  : apply the generated configs
SystemCoreClockUpdate
SetSystemClock()

 all clocks are disabled by default at startup.
use RCC->AHB1ENR to enable the clock of GPIO

the RCC is defined in  "stm32f4xx_rcc.h/c"

The RCC registers :

 

CR  (control register) :dis/enable /check clock sources.
CIR (interrupts ) : flags when clocks are ready.
CSR : flags
CFGR (clock configs ) : set switches and prescalers .
AHBxENR (clock enable ) : dis/enable clock for AHB.
APBxENR (clock enable ) : dis/enable clock for APB.
PLLGFGR (PLL config) : select source (ext/internal) and set NMPQ
DCKCFGR (PLL2-3 config)
SSCGR  spread spectrum config
AHB(1-3)RSTR  reset .
APB(1-2)RSTR  reset .
BDCR

AHB peripherals :

GPIO
USB OTG HS/FS
ETHERNET MAC
DMA1/2
RNG
HASH
CRYP
DCIM
FSMC

APB peripherals :

Timers (1-14)
USART (1-6)
UART (7-8)
I2C (1-3)
SPI (1-4)
CAN (1-2)
DAC
ADC
Watchdog
PWR
SDIO
LTDC


Clocks tree :

 Clock configuration tool